1. Field of the Invention
The present invention relates generally to the field of semiconductor capacitively coupled negative differential resistance (xe2x80x9cNDRxe2x80x9d) devices for data storage, and more particularly to reference cells to be used therewith.
2. Description of the Prior Art
U.S. Pat. No. 6,229,161 issued to Nemati et al., incorporated herein by reference in its entirety, discloses capacitively coupled NDR devices for use as SRAM memory cells. The cells disclosed by Nemati et al. are hereinafter referred to as thinly capacitively coupled thyristor (xe2x80x9cTCCTxe2x80x9d) based memory cells. FIG. 1 shows a pair of representative TCCT based memory cells 10 as disclosed by Nemati et al., and FIG. 2 shows a cross-section through one of the pairs of TCCT based memory cell 10 along the line 2xe2x80x942. FIG. 3 shows a schematic circuit diagram corresponding to the TCCT based memory cell illustrated in FIGS. 1 and 2. The TCCT based memory cell 10 includes an NDR device 12 and a pass transistor 14. A charge-plate or gate-like device 16 is disposed adjacent to, and in the case of the illustrated embodiment, surrounding, the NDR device 12. A P+ region 18 of the NDR device 12 is connected to a metallization layer 20 so that a first voltage V1, such as Vdd, can be applied to the NDR device 12 through the P+ region 18. An N+ region of the NDR device 12 forms a storage node 22 that is connected to a source of the pass transistor 14.
Successive TCCT based memory cells 10 are joined by three lines, a bit line 26, a first word line (WL1) 28, and a second word line (WL2) 30. The bit line 26 connects a drain 32 of pass transistor 14 to successive TCCT based memory cells 10. In a similar fashion, pass transistor 14 includes a gate 34 that forms a portion of the first word line 28. Likewise, the gate-like device 16 forms a portion of the second word line 30.
TCCT based memory cell 10 has both an xe2x80x9conxe2x80x9d state and an xe2x80x9coffxe2x80x9d state. In the xe2x80x9conxe2x80x9d state TCCT based memory cell 10 generates a current that is received by bit line 26. In the xe2x80x9coffxe2x80x9d state TCCT based memory cell 10 produces essentially no current. Second word line 30 is enabled to write a state to the TCCT based memory cell 10, while first word line 28 is enabled to read the state of the TCCT based memory cell 10.
FIG. 4 shows a representation of the voltage change on the first word line 28 during a read operation and the corresponding voltage change on the bit line 26. FIG. 4 illustrates that although the voltage on the first word line 28 (i.e., when pass gate 14 is enabled) rises rapidly to close the circuit at the pass transistor 14 to allow current from the NDR device 12 to reach the bit line 26, the voltage on the bit line 26 rises from ground much more gradually. More specifically, the bit line 26 has a capacitance, C, that is charged as current from the NDR device 12 begins to flow, and the pass transistor 14 has a resistance, R. Therefore, an RC time constant governs how quickly the bit line voltage can rise.
FIG. 5 shows a schematic circuit diagram of an exemplary reference cell 50 of the prior art. The reference cell 50 includes a pass transistor 52 coupled between an NDR device 54 and a bit line 56, and a charge-plate or gate-like device 58 disposed adjacent to the NDR device 54. The anode end 60 of the NDR device 54 and the gate-like device 58 are both coupled to a first voltage source 60 so that the NDR device 54 is continuously in the xe2x80x9conxe2x80x9d state. The pass transistor 52 includes a gate 62 coupled to a first word line 64. The pass transistor 14 (FIG. 3) has both a channel length, L, and a channel width, W, where L is the spacing between the source and the drain, and W is the width of the pass transistor 14 in the direction perpendicular to the page of the drawing in FIG. 2. Similarly, the pass transistor 52 also has a channel length, L, and a width, W. The ratio W/L for the pass transistor 52 is about half of the W/L ratio for the pass transistor 14. This is typically accomplished by producing a pass transistor 52 with about twice the length L of the pass transistor 14. Accordingly, reference cell 50 produces a reference current that is approximately half of the current produced by TCCT based memory cell 10 in the xe2x80x9conxe2x80x9d state.
FIG. 6 shows a comparison between the voltage on the bit line 26 (FIG. 3) and the bit line 56 (FIG. 5) as a function of time after their respective cells 10, 50 have been activated. It can be seen that although the current output from the reference cell 50 is less than that from the TCCT based memory cell 10, the voltages on the two bit lines 26, 56 eventually approach the same value. Accordingly, in the event that the TCCT based memory cell 10 is in the xe2x80x9conxe2x80x9d state and is selected to be read from, a sense amplifier comparing the voltages on bit line 26 (FIG. 3) and bit line 56 (FIG. 5) as a function of time will observe a difference (xcex941) that initially increases, reaches a maximum (xcex94MAX), and then diminishes again (xcex942). 
FIG. 6 does not include a curve to represent the voltage on the bit line 26 (FIG. 3) when the TCCT based memory cell is in the xe2x80x9coffxe2x80x9d state, as the voltage increase is negligible. It will nevertheless be appreciated that if the TCCT based memory cell 10 is in the xe2x80x9coffxe2x80x9d state, a sense amplifier comparing the voltages on bit line 26 (FIG. 3) and bit line 56 (FIG. 5) as a function of time will observe a difference that simply increases to a maximum since the voltage on bit line 26 is negligible. The problem for a sense amplifier trying to differentiate between the two states of a TCCT based memory cell 10 is that in both instances the difference between the two input voltages begins by increasing. Only be waiting a sufficient time does it become apparent whether the difference dissipates to indicate the xe2x80x9conxe2x80x9d state or does not dissipate to indicate the xe2x80x9coffxe2x80x9d state.
What is desired, therefore, is a reference cell for use with a TCCT based memory cell that can produce a voltage on a bit line such that a difference between the voltage and another voltage produced by the TCCT based memory cell on another bit line readily indicates a state of the TCCT based memory cell. It is further desired that the reference cell produce a voltage that rises at a rate that is proportional to the rate of increase of the voltage produced by the TCCT based memory cell to provide for fast and reliable sensing. It is also desired that the rate of increase for the reference cell be approximately half that for the TCCT based memory cell in the xe2x80x9conxe2x80x9d state.
A reference cell for a TCCT based memory cell includes an NDR device, a gate-like device disposed adjacent to the NDR device, a first resistive element coupled between the NDR device and a bit line and having a first resistance, and a second resistive element coupled between a current sink and the bit line and having a second resistance that is preferably about equal to the first resistance. In preferred embodiments the resistive elements are transistors and the gates of the transistors are both coupled to a first word line. In additional embodiments a second word line connects an anode of the NDR device and the gate-like device.
It can be seen that the reference cell of the invention is significantly like a TCCT based memory cell with the addition of the second resistive element, sometimes referred to as a pull-down resistor, between the current sink and the bit line. The addition of the second resistive element is advantageous because it allows for a reference cell that can produce a voltage increase on the bit line that rises proportionally to a voltage increase caused by a TCCT based memory cell.
A memory device of the invention includes a TCCT based memory cell and a reference cell. The TCCT based memory cell is configured to generate a first voltage on a first bit line and the reference cell is configured to generate a second voltage on a second bit line. The TCCT based memory cell includes a switching device, typically a pass transistor, having a first resistance. The reference cell includes first and second resistive elements, as described above. In some embodiments the resistances of the first and second resistive elements are about equal and about twice the first resistance. Other embodiments further include means for comparing the first and second voltages, for example, a sense amplifier.
The invention also includes a memory array including a plurality of TCCT based memory cells, at least one reference cell and a plurality of bit lines. The array can also include a sense amplifier to compare the voltages produced by the TCCT based memory cells and the reference cell. In embodiments of the invention the plurality of bit lines are arranged in parallel rows and each bit line has a number of the plurality of TCCT based memory cells attached thereto. The plurality of TCCT based memory cells may therefore be arranged as a matrix with one bit line per row. The reference cell in the memory array can be on a dedicated bit line, or several reference cells can be distributed around the array. In those embodiments in which reference cells and TCCT based memory cells share common bit lines, the array also includes a controller (not shown) containing logic required to select individual TCCT based memory cells and to select a reference cell on a different bit line.